It has long been recognized that numerous benefits may be derived by fabrication of semiconductor integrated circuits at very high integration density in which electronic elements such as transistors are formed with features that are of the minimum lithographically feasible dimensions. For example, close proximity of individual integrated circuit elements reduces signal propagation time (allowing higher clock speeds) and susceptibility to noise while allowing maximum functionality to be developed on a single semiconductor chip of practical dimensions at minimum cost, since the cost of required processes is not affected by the number of circuit elements concurrently formed.
However, as circuit elements such as transistors are reduced in size, a given design of, for example, a transistor or various functional portions thereof, such as a gate or gate insulator, may or may not be scalable (e.g. proportionally reduced or increased in size from a design of a similar device using a smaller or larger minimum feature size regime. In general, scaling of a transistor to a different size (and operation at a different nominal voltage which requires or is required by such scaling) will often affect such electrical parameters as switching threshold, breakdown voltage and leakage.
For that reason and some other practical considerations such as increased heat generation from increased numbers of transistors switching at increased clock rates, logic circuitry and memory structures of integrated circuits formed at extremely high densities are generally operated at much reduced voltages, often only a fraction of a volt, while currents are reduced by the reduced gate and connection capacitances achieved by such scaling and integration density. However, input signals to the integrated circuit and output signals developed in response thereto by the integrated circuit must be interfaced to external circuits and cannot be reliably operated at voltages and currents used by the logic circuitry and memory cells of the integrated circuit in order to achieve, for example, adequate noise immunity and to drive the capacitance and resistance of interconnection circuitry. Accordingly, transistors used for such input and/or output (I/O) connections that are capable of operating at higher voltages and currents but which must remain compatible with the transistors of the logic and memory of the integrated circuit (e.g. having switching thresholds scaled to approximately the same proportions of the nominal voltage swing) must also be formed on the chip. Such I/O transistors are generally of increased size and must have an increased breakdown voltage compared with the remainder of the transistors on the chip and yet, for economy of manufacture, are desirably formed using the same processes as the remainder of the transistors on the chip to the greatest extent possible. The I/O transistors must also meet stringent requirements for low leakage without affecting carrier mobility and so-called bias temperature instability (BTI) parameters. Conversely, it is desirable that the logic and memory transistors of the integrated circuit be electrically scalable from the I/O transistor design without increasing leakage or excessive reduction in breakdown voltage.
Unfortunately, such requirements are very difficult to achieve for different minimum feature size regimes. For example, use of a dual layer dielectric of a mixture of silicon oxide and silicon nitride (SiON) can be used to achieve a high breakdown voltage in I/O transistors but scaling of the inversion layer (a thin layer at the surface of the conduction channel adjacent the gate structure which is critical to high performance such as on/off resistance ratio, switching threshold, and switching speed/slew rate) is very difficult without compromising leakage and breakdown voltage.